The Effects of Arithmetic Encodings on SAT Solver Performance

As digital systems continue to grow, verification of these systems is becoming an increasingly important and difficult problem. To ensure a quick time-to-market, the verification problem must be addressed early in the design cycle. This requires the ability to verify systemlevel descriptions of hardware and embedded software systems, such as, C or Verilog, by proving assertions and proving functional equivalence. This can be done at the word-level by abstracting the word-level descriptions and proving equivalence or at the bit-level by converting the system-level descriptions into their equivalent boolean circuit representation and checking satisfiability. When verifying system-level descriptions of arithmetic functions at the bit-level, a verification engineer must choose how to represent the arithmetic operations in these functions. For example, if the arithmetic function being tested uses addition, the verification engineer will have to decide what type of adder he/she will use to represent the addition operation. Due to the fact that systems are becoming increasingly larger and more complex, verification needs to be as fast as possible. The encoding of a simple element like an adder may have a large effect on the runtime of the verification engine. With the recent advances in SAT solving, using SAT to verify the correctness of arithmetic assertions or functions at the bit-level may be a viable option. The goal of this project is to analyze and evaluate the performance of current state-of-the-art SAT solvers on arithmetic functions. More specifically, given assertions or functionality based on arithmetic operations, our goal is to determine which arithmetic encodings are “easier” to solve using a variety of SAT solvers.